• Speaker: Justin Gottschlich (Intel)
  • Date: October 31, 2013 (Thursday)
  • Room: CIT 368
  • Title: "Concurrent Predicates: A Debugging Technique for Every Parallel Programmer"
  • Abstract:
To reduce the complexity of debugging multithreaded programs, researchers have developed many techniques that automatically detect bugs that arise from shared memory errors. These techniques can identify a wide range of bugs, but it can be challenging for a programmer to reproduce a specific bug that he or she is interested in using such techniques. This is because these techniques were not intended for individual bug reproduction but rather an exploratory search for possible bugs. To address this concern we present concurrent predicates (CPs) and concurrent predicate expressions (CPEs), which allow programmers to single out a specific bug by specifying the schedule and program state that must be satisfied for the bug to be reproduced. We present the recipes, that is, the mechanical processes, we use to reproduce data races, atomicity violations, and deadlocks with CP and CPE. We then show how these recipes apply to the diagnosis and reproduction of bugs from 13 hand-crafted bugs, five real-world application bugs from RADBench, and three previously unresolved bugs from TBoost.STM, which now includes the fixes we generated using CP and CPE.

Justin Gottschlich is a Staff Research Scientist at Intel Labs, working in the Advanced Programming Research group. He is also an adjunct professor at the University of Colorado-Boulder and the CEO of Nodeka, LLC., a software company he founded over a decade ago. Justin has co-authored over twenty conference and workshop papers in the field of parallel computing. His primary research interests are in parallel programming, parallel algorithms, and transactional memory, with a specific emphasis on reducing the challenge of writing correct and efficient multithreaded software. Justin received his Ph.D. in 2011 from the University of Colorado-Boulder for his dissertation on optimizing software transactional memory systems.