Data-intensive algorithms are being widely adopted to solve many of today’s computational problems, introducing new challenges in designing efficient computing systems. Specialized hardware architectures are a promising approach to increase compute efficiency and are paving the way for such applications to be deployed to embedded devices. However, data movement remains a critical bottleneck and current CMOS memory technologies struggle to keep up with the increase in size and complexity for these critical workloads. As the future of computing is shaped by the way we store and process large amounts of information, there is a strong need for new memory systems that can enable denser, more energy-efficient on-chip storage. This talk will present application-driven design methodologies that leverage embedded non-volatile memories (eNVMs) as a dense, approximate storage solution to reduce off-chip DRAM accesses. In evaluating the implications of building eNVM-based computing systems, it is critical to take into account the non-idealities of many eNVM implementations. Multi-level cell storage offers the opportunity for higher capacity, but introduces reliability issues. Moreover, the high energy and latency costs of eNVM writes, together with limited memory endurance, set a limit on how frequently and efficiently the memory content can be updated. I will show that all these limitations can be circumvented by adopting cross-domain co-design optimizations, making eNVMs a viable solution for energy-efficient edge computing.